MPC5604 DSPI  TX/RX FIFO queue bytes size?

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MPC5604 DSPI  TX/RX FIFO queue bytes size?

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Zhimin
Contributor I

Dear Team:

                   MPC5604 DSPI  TX/RX FIFO queue bytes size?

TKS

 

 

Best Regards,

Atom

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

Which device did you mean?

There is 4-deep TX/RX FIFO on the MPC5604B and 5-deep TX/RX FIFO on the MPC5604P, MPC5604E.

BR, Petr

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Zhimin
Contributor I

hi,jive!

can read PC14 input level when config this pin as SPI1 MISO (my target iic is MPC5604B)?

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PetrS
NXP TechSupport
NXP TechSupport

the PC14 cannot be set as SPI1 MISO, did you mean PC4?

For the PC4 if SIU.PCR[36]. IBE bit is set you can read the input level from SIU.GPDI[36] register too.

BR, Petr

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Zhimin
Contributor I

TKS!

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Zhimin
Contributor I

MPC5604B

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