I am also facing the same problem. I am giving 3 chip select lines to the external decoder. The decoder will convert the 3 chip select lines in to 7 chip select lines. Hence, I want to control the either 1 or 2 or all 3 chip select lines simultaneously. Could you please let me know how I can do that. I am attaching the code what I am using at present. When I execute the below mentioned code then all the 3 CS lines are drawn simultaneously. This is an issue because in this case i cannot output the combination 011. Could you please let me know how can I solve the problem
param = QSPI_CS3;// QSPI_CS1;
printf ("Setting Chip select as CS3, CS2 and CS0 to %d ... ", param);
if (result == ioctl (fd, IO_IOCTL_QSPI_CHIP_SELECT, ¶m))
{
printf ("OK\n");
} else {
printf ("ERROR\n");
}
param = QSPI_CHIP_SELECT_SET_0;
ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, ¶m);
param = QSPI_CS2;
printf ("Setting Chip select as CS3, CS2 and CS0 to %d ... ", param);
if (result == ioctl (fd, IO_IOCTL_QSPI_CHIP_SELECT, ¶m))
{
printf ("OK\n");
} else {
printf ("ERROR\n");
}
param = QSPI_CHIP_SELECT_SET_0;
ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, ¶m);
param = QSPI_CS0;// QSPI_CS1;
printf ("Setting Chip select as CS3, CS2 and CS0 to %d ... ", param);
if (result == ioctl (fd, IO_IOCTL_QSPI_CHIP_SELECT, ¶m))
{
printf ("OK\n");
} else {
printf ("ERROR\n");
}
/* Bring CS low test*/
param = QSPI_CHIP_SELECT_SET_0;
ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, ¶m);
/* Bring CS high */
param = QSPI_CHIP_SELECT_SET_1;
ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, ¶m);
at the register level, you need to fill bits QSPI_CS (11-8) of the related QCR entries with the desired values.
Example: Need to pulse low CS0 during each transfer, and to pulse low CS1 during entry 7 and entry 15.
Passive CS is high level. First transfer at entry[0]. Last transfer at entry[15].
The needed values of QCR[0-15] bits:
QAR CONT QSPI_CS
---------------------------------------------------
0x20 0 0xE
0x21 0 0xE
0x22 0 0xE
0x23 0 0xE
0x24 0 0xE
0x25 0 0xE
0x26 0 0xE
0x27 0 0xC
0x28 0 0xE
0x29 0 0xE
0x2A 0 0xE
0x2B 0 0xE
0x2C 0 0xE
0x2D 0 0xE
0x2E 0 0xEHi Yevgenit
I am using the Freescale MQX RTOS Version 3.2. The Target processor is MCF52259 Cold fire 2 family. I want to use the external 3 to 8 decoder. The input to the external decoder will be CS0, CS2 and CS3. The output of the decoder will be the 7 chip selects based on the combination of the input chip selects For example.
CS3 CS2 CS0 Device
0 0 0 no Device Select
0 0 1 Device 1
0 1 0 Device 2
0 1 1 Device 3
1 0 0 Device 4
1 0 1 Device 5
1 1 0 Device 6
This functionality can only be achieved when I am able to control the chip selects pins simultaneously and change the status of the pins depending on the chip select line. I want to do it using MQX RTOS IOCTL routines.
Thanks
Atul
yosida ,
I am not familiar with MQX RTOS IOCTL routines. But, I believe, your API permits writing into QSPI registers.
Let CS outputs of QSPI controller are tied to the following address inputs of the regular 3-to-8 decoder: CS3 is tied to A2 input, CS2 is tied to A1 input, CS0 is tied to A0 input
The value is need to be filled into QWR[CSIV]: 0
The values are need to be filled into QCR:
QAR entry CONT QSPI_CS[3] QSPI_CS[2] QSPI_CS[1] QSPI_CS[0] selected
---------------------------------------------------------------------------------------
0x20 0 0 0 0 - 0 none
0x21 1 0 0 0 - 1 device1
0x22 2 0 0 1 - 0 device2
0x23 3 0 0 1 - 1 device3
0x24 4 0 1 0 - 0 device4
0x25 5 0 1 0 - 1 device5
0x26 6 0 1 1 - 0 device6
Note: above example isn't tested with actual hardware.