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Jlink connection not allowed after Flash Erase

Question asked by Emanuele Marraccini on Feb 14, 2017
Latest reply on Mar 7, 2017 by Emanuele Marraccini

Hi All,

I'm using Kinetis MK66FN2M0VMD18 on a Custom Board and I've some problems when performing Flash memory erase using Segger J-link tools (J-Link Commander, J-Flash, J-Flash Lite).

Sometimes after I've performed Flash Memory Erase I'm not able to establish J-link connection and I get the following message when I try to connect using some different tools ( J-Link Commander, J-Flash, J-Flash Lite ):

 --- Fatal Error: Kinetis (connect): Timeout while halting CPU. CPU does not stop. Session aborted!---


If I measure Reset pin voltage on the CPU using an oscilloscope I get a strange behavior when I apply power on: I observe a sawtooth similar signal, as the device is forced to reset state. It seems the device would be exit from reset state but Reset pin cannot reach high level (3.3V in our board) and is periodically forced to 0V.

Please note that in the default behavior when I connect the CPU using J-link the Reset pin goes to high level (3.3V).


After some tests I've been able to get back the CPU to normal behavior forcing reset pin to 0V while attempting to establish the connection using J-link Flash software.


I've looked for this issue and for its cause both on device documents and on the web but I've not been able to find an answer.


Although I'm able to resolve the situation I need to understand the cause of this issue in order to avoid it.

My application is safety critical and I need to avoid every maintenance operation on the field.


Could You please help me?


Best Regards.