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LS1043A SYSCLK/ DIFF_SYSCLK qur

Question asked by Logesh S on Feb 14, 2017
Latest reply on Feb 14, 2017 by Serguei Podiatchev

Hi,

 

We are using LS1043A, we are using 100MHz single ended output from SX3C18K25E-100.000MHZ from HMI with CMOS output Logic. We are planning to give this output as below,

 

Option 1:

Interface Connection
SX3C18K25E CLK OUTDIFF_SYSCLK
OVDD/2DIFF_SYSCLK_B

 

or

Option 2: Should we give single ended outputs only to SYSCLK and DDRCLK using two oscillators?

 

Note: SX3C18K25E-100.000MHZ, this oscillator is used only for system clock. For SERDES PLL1 and SERDES PLL2 we are using separate differential clocks.

PLL1  -  156.25 MHz 

PLL2  -   100 MHz (from differential clock buffer of our design)

 

1. Please Confirm which configuration should be used. If we are using first option we shall use only one oscillator. If we use the second option we need to use two oscillators.

2. Please suggest what type of terminations to be used in both options.
3. If option 1 is used kindly suggest the connection and termination values to be used in the design.

 

below is the link for SX3C18K25E-100.000MHZ datasheet,

http://www.hminternational.be/fiches/Oscillators/CMOS_Oscillators/sx3c.pdf 

 

Thanks

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