LS1043A SYSCLK/ DIFF_SYSCLK qur

[logeshs]

Hi,

We are using LS1043A, we are using 100MHz single ended output from SX3C18K25E-100.000MHZ from HMI with CMOS output Logic. We are planning to give this output as below,

Option 1:

Interface Connection
SX3C18K25E CLK OUT	DIFF_SYSCLK
OVDD/2	DIFF_SYSCLK_B

or

Option 2: Should we give single ended outputs only to SYSCLK and DDRCLK using two oscillators?

Note: SX3C18K25E-100.000MHZ, this oscillator is used only for system clock. For SERDES PLL1 and SERDES PLL2 we are using separate differential clocks.

PLL1  -  156.25 MHz 

PLL2  -   100 MHz (from differential clock buffer of our design)

1. Please Confirm which configuration should be used. If we are using first option we shall use only one oscillator. If we use the second option we need to use two oscillators.

2. Please suggest what type of terminations to be used in both options.
3. If option 1 is used kindly suggest the connection and termination values to be used in the design.

below is the link for SX3C18K25E-100.000MHZ datasheet,

http://www.hminternational.be/fiches/Oscillators/CMOS_Oscillators/sx3c.pdf 

Thanks

[r8070z]

Have a great day,

The LS1043A Design Checklist rev.2 available on the nxp site for the DIFF_SYSCLK says "when used, these  pins should be connected to a 100MHz differential clock generator" (see Table 43). Hence the SX3C18K25E CLK OUT should be connected to the SYSCLK. Of course in this case you need also apply clock to the DDRCLK. I.e. you implement Option 2. For Option 1 you need for a differential clock generator instead of the SX3C18K25E.

For Option 2 reset configuration pins IFC_OE_B and IFC_OE_B should be sampled as high on PORESET_B negation. They have internal weak pull-up so ensure that connected external device(s) do not pull down it that time.

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