Dear NXP engineers,
My system is,
- MPC5777C with C55 Flash
- System operating clock : 264MHz
- App : Bootloader with UDS
- Note. Data cach and Instruction cache are always enabled during startup sequence.
I assigned Stack area into the data cache through below code. It is our oem's request, mandatory.
# dcbz r0,r3 # Establish address in cache for 32 bytes and zero
# dcbtls 0,r0,r3 # Lock the address into the cache
# se_addi r3,32 # Increment to start of next cache line (+32 bytes)
# e_bdnz lock_cache_loop_0 # Decrement the counter (CTR), branch if nonzero
I tested flash erase via NXP's flash driver and I found weird situation during flash erase.
And I implemented PIT ch3 ISR for periodic boot task every 6.25ms.
I could see the critical input exception handler is asserted when PIT ch3 ISR is enabled and then execute the flash erase api.
Below is MCSR when IVOR0 is invoked.
I though that the reason of this exception was caused by enabled data cache, So I tested this thing with disabled data cache, Also stack was moved to sram area. However I could see same problem...
I want to know the every interrupts should be whether enabled or disabled during flash erase or write for preventing a IVOR0.
Please let me know.