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LS1043A-RDB, outbound PCIe ATU

Question asked by Martin Etnestad on Feb 13, 2017
Latest reply on Mar 30, 2017 by Pavel Chubakov

Hi!

 

I am trying to understand how the outbound PCI address translation is configured in the device tree for the LS1043A-RDB, and how I can modify it to suit our needs.

 

In the device tree file fsl-ls1043a.dtsi in SDK 2, I found this:

pcie@3400000 {
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
...
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

As far as I can tell, this allocates 1 GB worth of address space space for memory.

However, the system memory map shows that a 32 GB address section is set aside for each of the three PCI Express controllers in this device.

Is there a particular reason why so little address space is allocated? Can we increase it from 1 GB?

 

Also, it is not clear to me why the address ranges are also offset by 1 GB:

- PCI base address: 0x40000000

- System memory base address: 0x40 0x40000000

 

Is there any reason not to start the address ranges at zero, like below?

- PCI base address: 0x00000000

- System memory base address: 0x40 0x00000000

 

In our application, we need at least twice as much memory address space, i.e., 2 GB.

I expect to simply have to change the last line in ranges to:

0x82000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000>; /* non-prefetchable memory */

This would start the addressing at 0, and doubles the size to 2 GB.

Is this safe to do?

 

Thank you in advance for any help and insight in this issue!

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