I'm working on a new design where we use the MPC5674F EBI to connect an FPGA in 16-bit muxed data/addr mode (D_ADDR_16_31 routed to FPGA).
The FPGA behaves just like a SRAM from the cpu point of view, and we have an assembled prototype already.
Reading trough the datasheet, ref. manual or the External_Bus_Interface_FAQs_draftC.pdf documents didn't clarified this to me.
UserMan section "188.8.131.52 Size, Alignment and Packaging on Transfers" states:
• 16-bit access, address bit 31 must be 0, and
• The EBI never generates a misaligned external access
Our expectation is that we could map 64Kaddr (128Kbytes) on the FPGA, but our current tests show that we cannot access odd addresses on the EBI.
Is that a real limitation of this microcontroller or am I doing something wrong?