iMX6SL Unable Boot from eMMC

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iMX6SL Unable Boot from eMMC

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yakovshaulov
Contributor II

Hello everyone, 

We finally succeeded to load the Kernel. We’re also able to turn our device to Mass Storage mode and flash the U-Boot, Kernel and System Files to eMMC (we made Porting BSP from IMX6SL-EVK to our custom board).

Our custom board had PF3000 PMIC (instead of PF0100 as on IMX6SL-EVK board), LPDDR2 8Gb and eMMC v5.0 4GB (Micron MTFC4GACAJCN-1M WT) as boot memory device on USDHC2 port (instead of SD-card slot, that doesn’t exist on our board). On our board we don’t have access to BOOT_CFG GPIOs.

Our next stage was to programming the eFUSEs to boot from the eMMC. We use MFGTool to load and write the U-Boot, Kernel and File System to the eMMC but we unable to boot from the eMMC. We tried to set the eFuse (CFG1 & CFG2) as following:
Once with the value 0xC870 (Board 1) –
            BOOT_CFG1[4]=1 Fast Boot Support: Fast Boot
            BOOT_CFG1[3:2]=00 MMC Speed Mode: High Speed Mode
                                                                                 eMMC Fast Boot Acknowledge enable
            BOOT_CFG2[7:5]=110 Bus Width: 8-bit DDR (MMC 4.4)
            BOOT_CFG2[4:3]=01 Port Select: USDHC2
            BOOT_CFG2[2]=0 Boot Frequencies: 792/400 MHz
            BOOT_CFG2[1]=0 SD2 Voltage Selection 3.3V

And once (on another identical board) with the value 0x4860 (Board 2) –
            BOOT_CFG1[4]=0 Fast Boot Support: Normal Boot
            BOOT_CFG1[3:2]=00 MMC Speed Mode: High Speed Mode
                                                                                 eMMC Fast Boot Acknowledge enable
            BOOT_CFG2[7:5]=010 Bus Width: 8-bit
            BOOT_CFG2[4:3]=01 Port Select: USDHC2
            BOOT_CFG2[2]=0 Boot Frequencies: 792/400 MHz
            BOOT_CFG2[1]=0 SD2 Voltage Selection 3.3V

In both cases we unable to boot at power up! We don’t see any response on terminal screen (UART1 Port). In first case, the device turns to HID-Compliant Device after about 20sec. It seems like a CPU and eMMC tried to communicate on a power-up stage. We also see the CMD line (between MCU and eMMC) going from high to low after 83 usec and activity on CLK line in about 3 sec (at 50MHz frequency).
In second case, our board jumps immediately to HID-Compliant Device and there is no activity on CLK line and the CMD line never goes high.
Q(1): May it occurred as result of incorrect eFUSE programming?

We also tried to configure the PARTITION_CONFIG Register (EXT_CSD [179]) from MFGTool U-Boot command line as following:
            => mmc partconf 0 1 1 1
                        ‘0’ – mmc0 device
                        First ‘1’ (from left) - BOOT_ACK: Boot acknowledge sent during boot operation
                        Second ‘1’ - BOOT_PARTITION_ENABLE: Boot from boot partition 1
                        Third ‘1’ - PARTITION_ACCESS: R/W boot partition 1
  We noticed that this register is configured from emmc.c file with same configuration (after some debugging). But we still can’t boot from eMMC on power up.

However, on both boards we managed to boot the kernel from the eMMC after booting from MFGTool and using “boot” command from the MFGTool’s U-Boot command line. It seems like we have only issue with U-Boot booting from eMMC.
Q(2): Is this claim is true?

So the facts that we able to boot Kernel from eMMC (through MFGTool’s U-Boot) and have the ability to write and read from the eMMC eliminating the possibility of lack/fault of communication between iMX6 and eMMC.
Q(3): Is this claim is true?

Q(4): Does it mean that it impossible to boot with eMMC v5.0? Or it’s something else that we’re missing?

Q(5): What can be reason for the disability of booting from eMMC in our case?

As I mentioned, we stacked at boot from eMMC stage and we don't have any idea what can be reason for this issue. It seems like that we performed all steps correctly.

Regards

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yakovshaulov
Contributor II

Update:

I think we're realized what can be the source of the problem. We used mmc-utils on kernel with next command:

    mmc extcsd read /dev/mmcblk0

This command shows values of all eMMC registers. One of those registers is a PARTION_CONFIG. So we found that the value of this register is 0x48:

   Boot configuration bytes [PARTITION_CONFIG: 0x48]
      Boot Partition 1 enabled
      No access to boot partition

So, it seems like this is the source of disability to boot from eMMC. Is it right? 

As we understood the value of this register should be 0x49 in order to get access to to boot partition. 

So we tried to configure this register, but there is only boot_partition, send_ack and device bits that we can change:

   mmc bootpart enable <boot_partition> <send_ack> <device>

                   Enable the boot partition for the <device>.

                   To receive acknowledgment of boot from the card set <send_ack>

                   to 1, else set it to 0.

No PARTITION_ACCESS bit is present in this function, so we unable to change it to  R/W boot partition 1 value.

I want to note that we can change the value of the register, but only boot_partition and send_ack bits.

Is there a way to modify this register and whether it will solve our problem?

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Yuri
NXP Employee
NXP Employee

Hello

  Please look at my comments regarding the issue.

 

1.

  There is unpublished yet i.MX6 SL boot issue ERR007926/7ROM - 32 kHz
internal oscillator timing inaccuracy may affect SD/MMC and OneNAND boot. One can use the recent i.MX6 SL rev. 1.3 to avoid it or apply the following workarounds :

 

  1.1. Extend the assertion of POR_B until the 32 kHz crystal oscillator is running and stable.

  1.2. Provide an external stable 32 kHz clock input prior to de-assertion of POR_B.

 

2.

  Please try do not use the eMMC fast boot option (BOOT_CFG1[4] = 0). Then the eMMC card will be reset by the software command (CMD0).

 

3.

  Is LPDDR2 frequency low / equal 400 MHz in boot configuration ?
More high frequencies are not supported . Is the recent i.MX6SL LPDDR2
Register Programming Aid used for memory initialization sequence ?

 

< https://community.nxp.com/docs/DOC-105968 >

 

 

4.

Did you make the change to mmc.c and recompile u-boot (as per the mention in DOC-332187)?

 

“EMMC 5.0 and EMMC 5.1 work on i.MX6”

 

< https://community.nxp.com/docs/DOC-332187 >

 

  Is U-boot prepared for eMMC ? Please refer to section 5.5 (U-Boot configuration) of “i.MX_Yocto_Project_User's_Guide.pdf”.

   As for boot partition, please look at section 4.7.1 (Running Linux OS from MMC/SD) of

“i.MX_Linux_User's_Guide.pdf”.

 

< http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS >

 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!

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yakovshaulov
Contributor II

Hello Yuri,

Unfortunately I didn't get the answers to my questions, but only general recommendations for solving "Booting from eMMC" problem.

However, we double checked your comments and that is what we have:

1. 

      1.1: We can't extend the assertion of POR_B cause this signal is drives by PF3000 PMIC and the assertion time can't             be modified.

      1.2: We do provide stable 32.768 KHz clock.

   We also tried to extend the assertion time manually (by connecting the POR_B signal to GND for about 1 sec at    power- up) but it didn't help at all.

2. We used the FAST Boot option only once (on board 1 - see my comments above on this post). On the other cases, we used  once Normal BOOT with 8-bit Bus width and once Normal BOOT with 8-bit DDR Bus Width. We don't see any response from any of this options. However, in first case we saw CLK activity for about 3 sec (as I mentioned above) and  in a third case we saw CLK activity for about 122msec and some activity on CMD line. This activity (on CMD line) was repeated for several times in this122msec time window. The CLK frequency in this case is about 400KHz.

3. The LPDDR2 frequency is 400MHz. We ran the DDR Stress Test and modified the imximage.cfg file in accordance with the results obtained from the Test running.

4. The changes you're talking about should be implemented in Kernel L3.10. In our case, we using the Kernel L4.1.15_2.0.0 and the mmc.c file also modified for eMMC v5.0. 

The U-Boot is prepared for eMMC.

So, as I mentioned before, this is our only issue and we stuck on this for a long time. We need someone who can advise us and explain what could be the right solution. So can I talk with you or any other by phone? We don't see any other option.

Regards.

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aliismail
Contributor IV

Hi Yakov,

Did you get anywhere with this? I am having the same issue. I am not sure how to modify this register value.

Thanks!

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