using FCRDIV to get to 4 Mhz in VLPR mode on the Kinetis K65.
Upon bootup while in FEI state I set MCG_SC_FCRDIV(0).
The code then transitions to RUN mode running of an external oscillator.
Our code will transition into and out of VLPR mode from the run mode depending if there is processing that needs to be done.
Whenever we go into VLPR mode running off the internal 4 Mhz clock we only see a clock out of 2 Mhz. It acts like my setting of FCRDIV is not working. If I set it to zero the divider should be 1 and then I should see a 4 Mhz output.
While in VLPR the SIMDIV has been set to 0 for core, system, and flexbus. That means there is no divider on MSGCLKOUT. The flash clock is set to make sure the flash clock restriction is met while in VLPR.