Requirement of Serdes Reference Clock in P5040 Processor

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Requirement of Serdes Reference Clock in P5040 Processor

Jump to solution
556 Views
prasantahalder
Contributor II

Hi,

We need to use two x1 PCIe and four SGMII of P5040. For that we are planning to use SRDS_PRTCL=04h and we connected two serdes lanes(SD4-SD5) for PCIeand four serdes lanes(SD6-SD9) as SGMII. We are not using Serdes Bank-2, Bank-3 and Bank-4.

For this configuration we are feeding 100MHz clock only in SD_REF_CLK1_N/P while other reference clocks are grounded. Is this scheme is OK or should we provide clock in other reference clock inputs?

Regards,

Prasanta

Labels (1)
0 Kudos
1 Solution
408 Views
ufedor
NXP Employee
NXP Employee

> For this configuration we are feeding 100MHz clock only in SD_REF_CLK1_N/P

> while other reference clocks are grounded.

This configuration is viable.

View solution in original post

0 Kudos
1 Reply
409 Views
ufedor
NXP Employee
NXP Employee

> For this configuration we are feeding 100MHz clock only in SD_REF_CLK1_N/P

> while other reference clocks are grounded.

This configuration is viable.

0 Kudos