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Requirement of Serdes Reference Clock in P5040 Processor

Question asked by prasantahalder on Feb 9, 2017
Latest reply on Feb 10, 2017 by ufedor



We need to use two x1 PCIe and four SGMII of P5040. For that we are planning to use SRDS_PRTCL=04h and we connected two serdes lanes(SD4-SD5) for PCIeand four serdes lanes(SD6-SD9) as SGMII. We are not using Serdes Bank-2, Bank-3 and Bank-4.



For this configuration we are feeding 100MHz clock only in SD_REF_CLK1_N/P while other reference clocks are grounded. Is this scheme is OK or should we provide clock in other reference clock inputs?