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iMX6 Solo Dual Lite Camera Preview

Question asked by Soumya KS on Feb 7, 2017
Latest reply on Feb 8, 2017 by Soumya KS


Hi All,

I am trying to get a camera preview up using iMX6 Solo DualLite IPU. The Analog camera gives CVBS input to ADV7180 decoder. THe decoder gives 8-bit parallel CSI output to the IPU. THe IPU is connected to a tianna display. I am using iMX6 Platform SDK as the base. Below are the configurations I have created to get the camera preview. What should be the configurations for FLOW registers in my case? I am getting noise on the display. I see that the DMA is hapenning and I get a DMA EOF interrupt and Interrupt Status registers 9 and 10 are clear with no errors. Many thanks for the replies.

 

 //Init ADV 7180 registers

adv7180_init();

adv7180_swrite_reg (0x0C,0x37); //Put ADV7180 into Free Run mode

adv7180_write_reg (0x04,0x4E); //Output to BT656 mode

panel->panel_init(&ipu_index); //Init display panel 

 

//IDMAC Configuration for CSI->SFMC->MEM
   idmac_info.channel = CSI_TO_MEM_CH0;
   idmac_info.addr0 = csi_mem0; //CH23_EBA0 - 0x40000000
   idmac_info.addr1 = csi_mem1; // 0 - no double buffering
   idmac_info.width = in_fmt->active_width;
   idmac_info.height = in_fmt->active_height;   
   csi_pixel_format = INTERLEAVED_RGB565;

   ipu_general_idmac_config(ipu_index, &idmac_info);

   

//100 CSI1, ID=0 mapped to DMASMFC channel 0.
   ipu_smfc_fifo_allocate(ipu_index, 0, 4, 4);
   ipu_channel_buf_ready(ipu_index, CSI_TO_MEM_CH0, 0); //BUF_RDY

 

//CSI Configuration
   ipu_write_field(ipu_index, IPU_IPU_CONF__CSI_SEL, 1);
   ipu_write_field(ipu_index, IPU_IPU_CONF__CSI1_EN, 1);

   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_EN_POL, 0);

   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_EXT_VSYNC, 1);
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_PIX_CLK_POL, 0); // pos edge
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_POL, 0);
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_HSYNC_POL, hsync_pol);
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_VSYNC_POL, vsync_pol);

   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_DEST, 4); //destination is IDMAC via SFMC
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL, clock_mode); // Gated clock mode

   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_WIDTH, 1); //8bits per color
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_PACK_TIGHT, 0); //only when data format is RGB/YUV, and    data_width > 8
   ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_DATA_FORMAT, data_fmt);

   /*set sensor frame size */
   ipu_write_field(ipu_index, IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_HEIGHT, raw_height - 1);
   ipu_write_field(ipu_index, IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_WIDTH, raw_width - 1);

   

//setup display
ipu_display_setup(ipu_index, CH23_EBA0, (uint32_t) NULL, INTERLEAVED_RGB565, panel);

 

//Setup FLow

   ipu_write_field(ipu_index, IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL, 0x09); //DP_SYNC0 (ch23)
   ipu_write_field(ipu_index, IPU_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL, 0x9); // smfc0 -> chan23
   ipu_write_field(ipu_index, IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL, 0x1); // MG source from capture 0

 

   //Enable Display and capture

   ipu_enable_display(ipu_index);
   ipu_idmac_channel_enable(ipu_index, CSI_TO_MEM_CH0, 1);

 

Thanks and Best Regards,

Soumya 

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