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USB Peripheral in LPC11U24

Question asked by Timothy Masters on Feb 7, 2017
Latest reply on Feb 9, 2017 by jeremyzhou

Chapter 11 of the User's Manual for the subject chip (UM10462) provide information on the USB registers.  I have decided to write my own functions to service the USB due to lack of success with the USB API driver.

 

Here is my question relating to the following registers:

 

EPLISTSTART Register

Endpoint Command/Status List

The register is to be programmed with the start of the Endpoint Command List. The lower 8 bits are  assumed 00 since the list must be on 256 byte boundaries.  The LPC11U24 manual defines the USB RAM area at the following:

 

0x20004000 - 0x20004800  2Kbytes

 

Question:

Does this mean that this register should be initialized to 0x20004000? 

 

Application Description:

My device will be HID and have 2 endpoints inclusive of the Control Endpoint 0. I am going to limit the data IN and OUT payloads to 8 bytes in both the endpoints.  Endpoint 1 will be used in the Interrupt mode.  I will be managing the 8 byte payloads in firmware so only 8 bytes are needed in the buffer. For transactions requiring data lengths greater than 8, I will load the data in chunks of 8 bytes each and manage till the transaction is completed.

 

Question:

Can you define for me how the Endpoint Command/Status list needs to be initialized for my application? Particularly the EPX OUT and IN Buffer Address Offsets.  

 

Question: 

Are the Buffer Address Offsets from the location initialized in the EPLISTSTART register?  

Since the start list requires 0x4F bytes, does this mean the buffers should start at location 0x20004850?

 

DATABUFSTART Register

Question:

If the start location of the buffers is 0x20004850, how should the DATABUFSTART register be initialized?

I am not sure how to interpret the instruction in section 11.6.4 which states that this register indicates the page of the AHB address where the endpoint data can be located. Apparently only the top 10 bits are needed. 

 

Thanks

Tim

 

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