LS1043A Clocking Query

[logeshs]

Hi,

We are using LS1043A. We are using 

   - DIFF_SYSCLK/DIFF_SYSCLK_B input as 100MHz for internal clock

   - SD1_REF_CLK1_P/SD1_REF_CLK1_N input as 156.25MHz for XFI

   - SD1_REF_CLK2_P/SD1_REF_CLK2_N input as 100MHz for PCIe Gen2.0

My query is shall we provide SerDes clock inputs alone after the completion of processor boot up? After the processor has boot up we need to use Lane 0 as XFI/SGMII (2.5G) and Lane [2:3] as PCIe for Gen2.0 operation.

Please confirm that whether SerDes clocks are necessary for Processor boot up?

Thanks

[ufedor]

Which SerDes protocol is in question?

[logeshs]

Both the SerDes XFI/SGMII (PLL1) and PCIe (PLL2). shall we provide clock for both PLL1 and PLL2 after processor boot up?

[ufedor]

The reference clocks must be provided before PORESET_B deassertion and be stable during the processor operation.