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LS1043A Clocking Query

Question asked by Logesh S on Feb 2, 2017
Latest reply on Feb 3, 2017 by ufedor



We are using LS1043A. We are using 

   - DIFF_SYSCLK/DIFF_SYSCLK_B input as 100MHz for internal clock

   - SD1_REF_CLK1_P/SD1_REF_CLK1_N input as 156.25MHz for XFI

   - SD1_REF_CLK2_P/SD1_REF_CLK2_N input as 100MHz for PCIe Gen2.0


My query is shall we provide SerDes clock inputs alone after the completion of processor boot up? After the processor has boot up we need to use Lane 0 as XFI/SGMII (2.5G) and Lane [2:3] as PCIe for Gen2.0 operation.


Please confirm that whether SerDes clocks are necessary for Processor boot up?