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Controversial information about HDLC in different documents from NXP

Question asked by Sergey Gordienko on Feb 3, 2017
Latest reply on Feb 8, 2017 by Sergey Gordienko

Hi!

I'm trying to understand what HDLC modes are supported in different processors and I'm really confused.

For example, in QuiccEngine reference manual 7/2015 it's mentioned that for P1021/P1025/P1016/P1012 HDLC "Supported, but the ratio between the HDLC interface serial clock frequency and the QUICC Engine clock
frequency should be at least 1:14" (Chapter 14,p.1). In P1025 reference manual  (rev1. 01/2013) it's said: "The ratio between the HDLC interface serial clock frequency and the QUICC Engine clock frequency should be at least 1:3" (p.1630).

Another example: in QuiccEngine ref manual 11/2015 there is an information that LS1021A,LS1020A support HDLC, in 7/2015 QE ref manual LS1021A, LS1020A are not listed in Table 14-1 at all, and from LS1021A datasheet (11/2016) I know that LS1021A supports HDLC, but lite version (synchronous HDLC isn't supported).

I got an answer for my question "Full-featured HDLC-ports on ref boards with communication processor", but MPC830x kit that supports synchronous full-duplex HDLC-interface is obsolete and MPC8309 is obsolete too. NXP suggests to migrate to QorIQ processors, so it doesn't make sense to use MPC8309 for a new design. 

In TWR P1025 board there are 2 HDLC ports, but from Table 5-2 "I/O Connectors and Pin Usage Table" it's clear that there are no HDLC clock signals on the connectors, only RxD,TxD, CTS,RTS,CD!  However, from P1025 ref manual (1/2013, p.71) we know that not only async HDLC is supported, but full-duplex with data rates up to 50Mbps. It's so frustrating... Is it possible to assign some GPIOs from QE SerialExpansion group of the TWR-P1025 board's connector as in and out clocks for sync HDLC?

What is BISYNC HDLC and how it works? Is it described in any document?

Sorry, but I just can't understand an overall concept of QE and sync HDLC (where to get/how to form Rx/Tx clocks, do I have to assign HDLC Rx/Tx clocks to GPIOs or there are dedicated clock pins, is it possible to use CTS/RTS from async HDLC/UART to flow control while sync HDLC is used, how to configure QE in P1025 to use sync HDLC). Hope to get some explanation from you.

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