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Mismatch of reset value in i.MX27

Question asked by ko-hey on Feb 2, 2017
Latest reply on Mar 23, 2017 by ko-hey

Hi all

 

Let me confirm about the reset value in i.MX27.

 

I read chapter 3 of MCIMX27 Multimedia Applications Processor Reference Manual (MCIMX27RM Rev. 0.4 06/2012).

 

Q1

0x1002_700C (SPCTL0) SPLL Control Register 0
The reset value of Table 3-4 and Figure 3-7 doesn't match. Which is correct ?

 

Q2

0x1002_7018 (PCDR0) Peripheral Clock Divider Register 0
The reset value of Table 3-4 and Figure 3-10 doesn't match. Which is correct ?

 

Q3

0x1002_701C (PCDR1) Peripheral Clock Divider Register 1
The reset value of Table 3-4 and Figure 3-11 doesn't match. Which is correct ?

 

 

Ko-hey

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