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S12XDP/XEQ Self Clock Mode

Question asked by Tarcisio Julio de andrade on Feb 2, 2017
Latest reply on Feb 9, 2017 by Daniel Martynek

I use the S12XDP512 and S12XEQ512 and I'm having many problems with clock locking in the field, when my device is already running.

 

I use a 4MHz crystal and pll to reach pllclk = 80MHZ and busclk = fpll / 2

 

S12XEQ512 config:

CRGINT = 0b00000010;

PLLCTL = 0b11001001;
REFDV = 0x40;
SYNR = 0x49;
POSTDIV = 0;
CLKSEL = 0b11000000;

 

S12XDP512 config:

CRGINT = 0b01000010;

PLLCTL = 0b11101001;

REFDV = 0;
SYNR = 9;

CLKSEL = 0b11000000;

 

My application works but in some cases there is a clock error and it goes into self clock mode.
  I configured the MCU to generate an interrupt in which I wait for the clock to stabilize:
  While (! CRGFLG_LOCK) {}
  CLKSEL_PLLSEL = 1;

 

In some cases this happens sporadically and the interruption is enough to resume normal operation.   But in other cases this happens very often, disrupting the operation of my application (e.g. messing with baudrates and serial communication).
 
I use the Full Swing Pierce Oscillator for the crystal circuit, but I do not have a pulldown resistor on the PE7 port to configure the MCU to use this oscillator circuit.
  I noticed that after booting it is always with /XCLKS = 0.

 

Shouldn't the problem only happen in the clock Initialization (not locking the clock) or can it happen in the middle of the operation too, after the initial lock?
What is the difference between the controlled pierce oscillator loop and the full swing pierce oscillator, in terms of Voltage noise and EMI tolerance?
Is there any other situation that can cause clock loss? Because it happens only in 10% of my equipment and I do not see any pattern that could cause the loss of the clock.
  
   Thank you.

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