Dear team,
My customer is trying to modify HSYNC and VSYNC duration of i.MX6Q LVDS output.
The customer’s development environment is as below.
Parts#: MCIMX6Q6AVT10AD
LVDS output: pixclock=27MHz(base clock: IPU1_DI0), 720x480 59.94Hz Interlace
OS: LinuxBSP(3.14.38)
The current low period of HSYNC/VSYNC is short and they want to expand them.
The customer wants to expand the low period of HSYNC to 45uSec.
And they want to expand the low period of VSYNC from the current one as well.
Could you show me which source code of the LinuxBSP and which bitfield should be modified for that?
Thanks,
Miyamoto
Please read this App. Note for reference.
http://cache.nxp.com/assets/documents/data/en/application-notes/AN3974.pdf
Although this is an old document for i.MX35, this document show you the timing concepts (section 2.4.1) and the details about what is fb_videomode().
So, you can find the display-timings setting for fb_videomode() in your_board.dtsi and then modify the values base on your needs.
For example:
in the i.mx6qdl-sabresd.dtsi (linux-2.6-imx.git - Freescale i.MX Linux Tree )
&ldb {
status = "okay"; lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};