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Question, i.MX6Q LVDS HSYNC/VSYNC timing tuning

Question asked by AVNET JAPAN FAE (team share account) on Jan 31, 2017
Latest reply on Feb 3, 2017 by jimmychan

Dear team,


My customer is trying to modify HSYNC and VSYNC duration of i.MX6Q LVDS output.

The customer’s development environment is as below.


LVDS output: pixclock=27MHz(base clock: IPU1_DI0), 720x480 59.94Hz Interlace

OS: LinuxBSP(3.14.38)

The current low period of HSYNC/VSYNC is short and they want to expand them.

The customer wants to expand the low period of HSYNC to 45uSec.

And they want to expand the low period of VSYNC from the current one as well.

Could you show me which source code of the LinuxBSP and which bitfield should be modified for that?