In IMX6UL reference EVK design, DDR3 data lines are swapped in memory device side. So we are having 4 questions related to it.
Q1. Is it mandatory to follow same EVK data line swapping connection to our Design? then why its required?
Q2. Do we connect DDR3 with out swapping data lines to Ultra lite processor DDR controller (D1 to D1, D2 to D2 ..... D16 toD16) for our new design, so what will be a problem?
Q3. We hope this Data line (bit) swapping done for Read/Write levelling through software. Am i right?
Q4. If we didn't do the Data swapping as per EVK in our design, NXP provided BSP will work in our design (or) we need to put extra software effort on it?
Could you please clarify us ASAP?
This is our new design using Ultra lite processor, so before we are going to FAB need to make sure this.
I have attached NXP EVK schematic snap shot and Our New design snapshot as well
Thanks & Regards,