AnsweredAssumed Answered

i.MX6 dual lite can not copy data to EIM NOR under uboot

Question asked by Andy Huang on Jan 26, 2017
Latest reply on Jan 26, 2017 by igorpadykov

Hi, 

We have a i.mx6 dual lite custom board with yocto 4.1.15_2.0 sdk + 32MB parallel nor flash.

I turn on the SYS_USE_EIMNOR flag  in the mx6sabresd_defconfig setting , so I can see the nor flash during booting.

I also can erase flash but can not cp.b to the nor flash.

 

It always pop "Copy to Flash... Flash not Erased" error.

 

 

U-Boot 2016.03-g3163ae6-dirty (Jan 26 2017 - 22:50:49 +0800)

CPU: Freescale i.MX6DL rev1.2 at 792MHz
CPU: Automotive temperature grade (-40C to 125C) at 35C

Reset cause: POR
Board: MX6-SabreSD
I2C: ready
DRAM: 256 MiB
Flash: 32 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1 is current device
Net:
board_eth_init
Board Net Initialization Failed
No ethernet found.
Normal Boot
Hit any key to stop autoboot: 0

=> erase all
Erase Flash Bank # 1
........................................................................................
........................................................................................
................................................................................ done

=> flinfo

Bank # 1: CFI conformant flash (16 x 16) Size: 32 MB in 256 Sectors
AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x227E2201
Erase timeout: 2048 ms, write timeout: 1 ms
Buffer write timeout: 3 ms, buffer size: 1024 bytes

Sector Start Addresses:
08000000 08020000 E 08040000 E 08060000 E 08080000 E
.

.

.


09F40000 E 09F60000 E 09F80000 E 09FA0000 E 09FC0000 E
09FE0000 E
=> fatload mmc 1:1 ${loadaddr} u-boot.imx
reading u-boot.imx
407320 bytes read in 40 ms (9.7 MiB/s)
=> cp.b ${loadaddr} 0x8001000 ${filesize}
Copy to Flash... Flash not Erased

=> mw.l 0x8000000 0x12345678
=> md.l 0x8000000 1
08000000: ffffffff

=> clocks
PLL_SYS 792 MHz
PLL_BUS 528 MHz
PLL_OTG 480 MHz
PLL_NET 50 MHz

IPG 66000 kHz
UART 80000 kHz
AHB 132000 kHz
AXI 198000 kHz
DDR 396000 kHz
USDHC1 198000 kHz
USDHC2 198000 kHz
USDHC3 198000 kHz
USDHC4 198000 kHz
EMI SLOW 99000 kHz
IPG PERCLK 66000 kHz

 

 

 

EIM CS0 setting

writel(0x10020181, &weim_regs->cs0gcr1); 
writel(0x00000001, &weim_regs->cs0gcr2);
writel(0x0a020000, &weim_regs->cs0rcr1);
writel(0x0000c000, &weim_regs->cs0rcr2);
writel(0x0804a240, &weim_regs->cs0wcr1);
writel(0x00000120, &weim_regs->wcr);

Outcomes