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MQX 4.2 SPI Master/Slave: first frame received with delay

Question asked by Goncalo Andre on Jan 26, 2017
Latest reply on Feb 15, 2017 by soledad

Hello,

 

I'm implementing a SPI slave module for the Kinetis K60FX512, running with MQX 4.2 (I'm using the new SPI drivers in full-duplex mode). To test it I've set up a SPI master and a slave on different SPIx accesses, each running on a dedicated task, and connected the pins externally and set-up a very slow clock (5 KHz).

The slave prepares its transmit buffer, and the spi driver eventually calls the _dspi_tx_rx() function, that pushes it to the bus and blocks (it is configured to use ISR) until the message from the master is received.

After that the master is initialized, prepares its transmit buffer, and the function _dspi_tx_rx() pushes it to the bus and simultaneously tries to read what the slave sent. The problem is that nothing on the first frame is transmitted by the slave, instead the first frame sent by the slave is only transmitted during the execution of the second frame. All further frames are then transmitted by the slave with a delay of one (the last frame of each message is sent as the first of the following) - see attached picture. This does not happen in the other direction, i.e. the master sends its frames on time, and are thus read timely by the slave.

I've compared the behaviour with another application where the K60 controls as a master an external peripheral, and this does not happen, i.e. the first frame from the slave is received as the first frame from the master is sent. I've tried to manually match the register configuration of both cases at the entrance of the _dspi_tx_rx() function, to no avail.

 

Any tips to solve this problem would be gratly appreciated. Thanks.

Goncalo.

 

SPI Configuration:

Master: 

SPI0,

SPI MODE 0 (CPHA=0, CPOL =0),

8 bit Frame size,

BIG ENDIAN

CS=0 (I control the CS pin manually),

0xFFFFFFFF Dummy pattern,

DMA Disabled

 

Slave: SPI2,

SPI MODE 0 (CPHA=0, CPOL =0),

8 bit Frame size,

BIG ENDIAN

USE ISR,

CS=0,

0xFFFFFFFF Dummy pattern,

DMA Disabled

 

Attachement 1: First message transmitted on SPI bus. CH1: SCK, CH2: MISO. (Slave TXBUFF: 0x55 0x55 0x55 0x55)

Attachement 2: SPI register contents at end of first message transmitted (Just before master returns from _dspi_tx_rx() ).Master: SPI0, Slave SPI2. Master sends: 0x41 0x00 0x00 0x00. Slave sends: 0x01, 0x02 0x03 0x04.

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