I try to configure USB 3.0 controller on an ls1043ardb. I use a stack that already working
on x86 real and virtual targets. On these architecture xHCI controller is accessed through PCI.
I try to port this stack on arm-v8 architecture.
Documentation (QorIQ LS1043A Reference Manual, Rev. 2, 11/2016)
seems pretty poor concerning initialization of DWC3 register set.
There is something in "184.108.40.206.4.1 Initializing global registers" but it doesn't describe
the process and values to be set in registers for host mode.
Except u-boot driver or linux kernel driver there is no explanation about
how this controller works..
For the moment, when a device in plugged in USB1 connector linked to USB1 controller
PORTSC_PR bit is written in PORTSC register and an IRQ is received with bits
USBSTS_PCD and USBSTS_EINT set in USBSTS register.
Moreover IP bit is set in IMAN (0 for interrupter 0). So every seems all right except.. event ring.
The problem comes from *event ring* that creates *no* event.. xHCI controller
is supposed to generate a "Port Status Change Event TRB" (See xHCI specification revision 1.1
Do you know where I can find a documentation that explains how to configure
the USB 3.0 controller as *host only* properly?
I don't find something relevant in OTG chapter.