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i.MX7D - Why are upper/lower bytes of GPIO1 implemented differently?

Question asked by Bill Gessaman on Jan 25, 2017
Latest reply on Jan 29, 2017 by igorpadykov

This question is driven by trying to correctly understand how LPSR mode works and make sure our custom design will have the expected functionality to resume from LPSR.  Our design is based on the i.MX7D Sabre board with DDR3L memory and we are running Linux based on L4.1.15-1.0.0GA.  I'm using Rev 0.1 of the Reference Manual.


In the LPSR Mode section of the RM it says - "In LPSR mode, the supported wakeup source are RTC alarm, ONOFF event, security/tamper and also the 16 GPIO pads."  We happen to have both NVCC_GPIO1 and NVCC_GPIO2 connected to LDO3 in the PF3000 so we have adjusted the PMIC programming to leave LDO3 on in LPSR mode.  Then I notice that the lower 8 bits of GPIO1 are implemented by the IOMUX LPSR block and the upper 8 bits are implemented in the larger IOMUXC block.  Why this asymmetry in the implementation if all 16 bits are available as wakeup sources in LPSR?


Additionally, there are two registers (IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20 and IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21) in the IOMUXC_LPSR_GPR memory map that implement alternate pad control for the upper 8 bits of GPIO1.  There is no explanation as to why this is available and I can find nothing in the BSP that makes use of these extra pad control bits in these two GPR registers.  Does anyone have knowledge about why the implementation is different?  I can't imagine that this is a case of having to hide information in the Security Reference Manual.



Bill Gessaman