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VESA display timing on i.MX6UL

Question asked by Paul Schoenke on Jan 25, 2017
Latest reply on Feb 20, 2017 by Yuri Muhin

I have a design with the i.MX6UL and am trying to and change the display timings to a standard VESA aspect such as the following, but I'm not getting the proper timing output that I would expect:


                                                timing0 {

                                                clock-frequency = <40000000>;

                                                hactive = <800>;

                                                hfront-porch = <40>;

                                                hsync-len = <128>;                                          

                                                hback-porch = <88>;

                                                vactive = <600>;                                               

                                                vfront-porch = <1>;

                                                vsync-len = <4>;

                                                vback-porch = <23>;                                       

                                                hsync-active = <0>;

                                                vsync-active = <0>;

                                                de-active = <1>;

                                                pixelclk-active = <0>;



With the above settings, when we measure the pixel clock, we get 36 MHz instead of 40 MHz, similar ~10% errors at 640x480 and 1024x768).


The numbers above were produced correctly except for the clock frequency and the slower clock frequency also generated lower display refresh which it was at 54Hz instead of 60Hz due to slower pixel clock.  It has to do something with PLL setting in order to generate proper PLL clock.


Any feedback or input is welcomed and appreciated!