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IMX6SDL IPUx_CSIx_VSYNC,HSYNC; active-high/low and rising/falling-edge triggered IPU_CSI_PIX_CLK.

Question asked by Takashi Takahashi on Jan 23, 2017
Latest reply on Jan 24, 2017 by igorpadykov

Dear community.

Our customer has question below.

 

IMX6SDLAEC P94 of 4.11.10.2.3 Non-Gated Clock Mode  describe that rising / falling edge and active HI / Lo can be changed,
Where should I refer to specific settings?

 

The timing described in Figure 61 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered
IPUx_CSIx_VSYNC; active-high/low IPUx_CSIx_HSYNC; and rising/falling-edge triggered
IPUx_CSIx_PIX_CLK.

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