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iMX7 Dual LPSR Mode implementation

Question asked by Sanchayan Maity on Jan 22, 2017
Latest reply on Jan 23, 2017 by igorpadykov

Hello,

 

I am working on Toradex Colibri iMX7D module and trying to validate the LPSR mode. The kernel is based on Freescale's 4.1.35 kernel. Am referring to the LPSR mode discussion on the community as a reference.

 

In the plugin.S assembler code, there are writes to register locations I cannot trace. For example, there is one here.

 

ldr r1, =0x30360000

<snip>

/* turn on ddr power */
ldr r7, =(0x1 << 29)
str r7, [r1, #0x388]

 

So the above piece of code, sets r1 to 0x30360000 where 0x30360000 to 0x3036FFFF is CCM Analog register space and then tries to set 29th bit at register 0x30360388. As per iMX7D reference manual Revision 0.1 dated August 2016 release I do not see a register at this location. The CCM Analog Memory map table in Section 5.2.9 shows locations from 0x30360060 to 0x3036017C.

 

This here seems to say 0x30360388 is SNVS_MISC_CTRL register

 

/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
ldr r7, =(0x1 << 30)
str r7, [r1, #0x388]
ldr r7, =(0x1 << 30)
str r7, [r1, #0x384]

 

but as per the iMX7D Security Reference Manual the SNVS_MISC_CTRL has a register location of 0x3400000C as shown in the table on Page 85 in SNVS memory map table.

 

Can someone clarify the above? Some of the register locations accessed by the plugin assembler code are either not documented or wrong either in TRM or the code? Which one is it?

 

Is there any proper documentation available on requirements of implementation for LPSR?

 

Regards,

Sanchayan.

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