I have a master/slave SPI setup between two microcontrollers, the master is a 68H11A1, the slave a 9S12E64's, we use a line called MODULE_ENn for slave select (SS_bar). The master runs from an 8MHz external oscillator, so 1MHz SPI (SCK). I currently have the 9S12 running from an 8Mhz crystal and communication is fine. The issue that I am having is power, the slave board has a quiescent current around 370uA, this is too high.
The majority of the current comes from the me not being able to enter full STOP mode. I cannot enter STOP because I have to encounter the clock quality check upon wakeup from STOP. The micro’s IRQ is tied to the MODULE_ENn (SS_bar) line, so it needs to wakeup when selected and grab the commands from the SPI data register quickly enough so that it doesn’t miss any. There simply isn’t enough time to wakeup from a full STOP to receive the 1st byte because of the clock quality check, so I have to stay in PSEUDO-STOP mode. There are 120uS from the IRQ (SS_bar) to the first 1MHz SCK.
My solution is to run the 9S12 at a lower speed, hopefully cutting the quiescent current by around half. My question first question is, what is the min clock frequency that I can run a 9S12 in SPI slave mode and still be able to receive messages coming in at 1Mhz? I have seen the SPI specs for master mode, but my question is about slave.
Looking at the SPIV3 block diagram, I see that the SPI data register is dependent on both the shift and sample clocks. How many core clocks are required after the data is shifted into the SPI data register (8th SCK tick) until the data is possible to be read?