Max SPI Slave Speed 9S12E64

[ajacks504]

Hello,

I have a master/slave SPI setup between two microcontrollers, the master is a 68H11A1, the slave a 9S12E64's, we use a line called MODULE_ENn for slave select (SS_bar).  The master runs from an 8MHz external oscillator, so 1MHz SPI (SCK).  I currently have the 9S12 running from an 8Mhz crystal and communication is fine.  The issue that I am having is power, the slave board has a quiescent current around 370uA, this is too high.

The majority of the current comes from the me not being able to enter full STOP mode.  I cannot enter STOP because I have to encounter the clock quality check upon wakeup from STOP.  The micro’s IRQ is tied to the MODULE_ENn (SS_bar) line, so it needs to wakeup when selected and grab the commands from the SPI data register quickly enough so that it doesn’t miss any.  There simply isn’t enough time to wakeup from a full STOP to receive the 1st byte because of the clock quality check, so I have to stay in PSEUDO-STOP mode.  There are 120uS from the IRQ (SS_bar) to the first 1MHz SCK.

My solution is to run the 9S12 at a lower speed, hopefully cutting the quiescent current by around half.  My question first question is, what is the min clock frequency that I can run a 9S12 in SPI slave mode and still be able to receive messages coming in at 1Mhz?  I have seen the SPI specs for master mode, but my question is about slave.

Looking at the SPIV3 block diagram, I see that the SPI data register is dependent on both the shift and sample clocks.  How many core clocks are required after the data is shifted into the SPI data register (8th SCK tick) until the data is possible to be read?

Thanks,

Adam

[bigmac]

Hello Adam,

If the SPI master clock rate is 1MHz, it would seem that the minimum allowable bus frequency for the slave end would be 4MHz.  For operation with a lower bus frequency, the SPI clock rate would need to be reduced.

For SPI slave operation, the critical timing is likely to be that required to derive any return data in response to the incoming byte, and to load the return byte value into the data register, all prior to the first clock edge of the next transfer, and possibly prior to the SS signal going low.

Regards,

Mac

[ajacks504]

Thanks Mac,

Yes, you are correct, the max SCK frequency for SPI is f_bus, I was pointed to this spec in the 9S12 data sheet by a Freescale apps guy.  Its in A5 (SPI Characteristics), table A-18.

I'm my case I am already running from an external 8 MHz XTAL, so my bus clock is 4 MHz, this tells me that I can't run the part and successfully recieve SPI transmissions from the master with a 4 MHz XTAL,

I'm going to start looing into self clocking mode, maybe I will be able to pump up the PLL in time to get my f_bus up to recieve the byte.  There is 120us from SS to the first SPI byte in the system I am working with (there is no way to change it's SPI settings, legacy product).

If only the **bleep** clock qualifier were capabale of being disabled like the the 68HC11!!!   I understand why its there, I just wish that with the right warnings, they would let the user disable it!