We are routing DDR3L signals and referring to HW development guide. In this we are routing the signals as per table, which is attached.
As shown in attached figure, does the bigger red circle represent minimum routing length should be Clock(min)-200mil?
As we are routing clock with 1400 mils, so we are allowed to route data and its control signals between 1200 to 1400 mils?
The other doubt is in smaller red circle. Does the dash --- represents the same recommendation to DRAM_D[15:8] are same as DRAM_D[7:0].