Serdes Lane/Signal assignment for SGm T2081

[christiankeller]

The T2080RM specifies Lane/Signal assignments for PCIem interfaces in table 19-2.

I am unsure how the SGMII interfaces relate to this and also this table is not referenced in the text.

Is there a similar table to get to the assignment for the SGMII interfaces?

And a second related question:

What's the relationship of lanes and slots in the U-Boot code when setting up the interfaces. Especially why assign all SGMII interfaces to slot 7, say, when SerDes is configured in config 0xf2?

I may just be confused about the different naming conventions. Maybe you can say something about this as well. (The naming, not my confusion).

Thanks,

Christian

[r8070z · Accepted solution]

Have a great day,

Each SGMII interface use only one serdes lane. The assignment for the SGMII you can find in the T2080RM Table 19-1. SerDes Lanes Assignments and Multiplexing. In this table SGm means SGMII @ 1.25 Gbaud SGm (italic font style) means SGMII @3.125 Gbaud, where "m" indicates which MAC on the Frame Manager. The Table 19-2 provides serdes lanes and signals relation for all protocols. For example, for SRDS_PRTCL_S1=0x1C Table 19-1 says that SG9 uses lane A and SG6 uses lane H. In according to the Table 19-2 it means that SG9 uses signals
SD1_TX[0]/SD1_TX[0]_B
SD1_RX[0]/SD1_RX[0]_B

and SG6 uses signals
SD1_TX[7]/SD1_TX[7]_B
SD1_RX[7]/SD1_RX[7]_B

I think you can find definition of “slot” in the U-boot code text. You wrote “when SerDes is configured in config 0xf2” if you mean that SRDS_PRTCL_S1=0xF2 then for sure it means the SG6 on the lane H i.e. SGMII uses SD1_TX[7]/SD1_TX[7]_B and SD1_RX[7]/SD1_RX[7]_B.

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