My question has two parts:
1. We have ODR set to 400 Hz. We have configured the FIFO to trigger (FMODE = 11) on pulse event with watermark in the middle of the 32-sample FIFO buffer. I think this implies that the 80 msec wide buffer has 40 msec from the pulse event (and watermark) to the time when the FIFO buffer is full and the interrupt is triggered. Is that correct, i.e., in FMODE = 11 is the interrupt generated not at the watermark but rather 40 msec later when the buffer is full?
2. For separate purpose, running concurrently, our firmware polls the most recent xyz-data sample at 50 Hz or every 20 msec (by reading the usual xyz-data register 0x01, not the FIFO buffer). When we have this code in place, and we read the FIFO buffer following the pulse interrupt, we see FIFO values of -8160 filling one or more samples at the end of the FIFO, and the data spike that generated the pulse event is shifted that number of samples from the watermark. Is it possible that reading 0x01 is corrupting the FIFO? Is there a way to configure and use the accelerometer so we can get both FIFO for each pulse event and also poll ordinary data stream from 0x01 concurrently?