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Soft reset LS1021A from Linux

Question asked by rahulr on Jan 16, 2017
Latest reply on Jan 18, 2017 by Daniel Amor martin

My understanding is that the Linux reboot command will cause a watchdog timeout to create the reset condition. Is there a Linux command to perform a core soft reset?


Section 4.4.3 (Core soft reset) of the LS1021A reference manual explains steps for soft reset. Since I am using Linux, do I need to manually manipulate registers and create ISRs if I were to write a tool for soft reset?

  1. Write '1' to SCFG_CORESRENCR[CORESREN], to enable the soft reset to the corresponding core.
  2. Write '1' to SCFG_CORE0_SFT_RST[SOFT_RESET] and SCFG_CORE1_SFT_RST[SOFT_RESET] to enable the soft reset to the core 0 and core 1 respectively. Writing '1' to these bits triggers the corresponding interrupt to respective cores (Interrupt ID 228 and Interrupt ID 229). The interrupts need to be configured as edge trigger interrupt.
  3. Perform the GIC interrupt mapping as follows:
    • Enable the interrupt.
    • Select edge trigger mode.
    • Route 228 to core 0 and 229 to core 1.
  4. In the core 0 ISR, set SCFG_CORE0SFTRSTSR[SFTRST] for the chip to recognize the soft reset to core 0 and execute WFI instruction.
  5. In the core 1 ISR, execute the WFI instruction.
  6. Once the cores execute WFI instruction, COP generates the corresponding core soft reset.