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iMX6UL/ULL LDO Bypass - allowed voltage ripple

Question asked by Markus Brandstätter on Jan 16, 2017
Latest reply on Jan 17, 2017 by igorpadykov



I assume that the iMX6UL is not really different from other members of iMX6x Family in the sense of this question, but I used iMX6UL in the header of this question because this is the processor I currently deal with.



I cannot find a quantitative specification about how big the voltage ripple of an external DC/DC can be, so that the iMX6UL can be safely used with the internal LDOs bypassed. I only find sentences like

"The voltage rails that have internal LDOs (core, PU, SoC) require very precise and accurate levels. An external switcher won't be able to provide such an accurate voltage due to its switching nature", which does not really help.



Also, looking at e.g. SPF-28617, I see that the common ARM/SOC rail "VDD_ARM_SOC_IN" is driven by a DC/DC switcher. In AN5170 one can see in Table 1, that the internal LDOs are indeed enabled for this hardware setup. However, what about the deepsleep mode in this case? The DVFS circuit used in this schematic seems to set the external DC/DC setpoint to 0.925V, which is just 25mV above the minimum VDD_SOC_IN voltage as specified in datasheet - however, the SOC LDO is bypassed in this usecase?


Thanks a lot!