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DDR3 i.mx6ul MT41K256M16TW-107 IT calibration issue

Question asked by Jakub Kuzilek on Jan 13, 2017

Hello, I´m working on new board and I have serious problem with testing of ddr3 memory. I spend about two weeks of changing registers and investigating memory timing with no luck. So I thought it´s bad layout of ddr3 bus, but my colleague accidentally changed MDOR register from 0x006B1023 to 0x006B1000 and memory starts working even stress test successfully passed. We are really confused about this setting because this value is reserved. I´m using ddr stress test v2.60 no change in script, just MDOR value.

Demoboard differences:

  • Layout
  • Power supply MC34PF3000A7EP
  • Crystal clk source

I also attach dump of registers from my colleague.

Can someone explain this behavior and recommend the correct setting of the memory controller?

Thanks

Original Attachment has been moved to: mmdc_dump1_cre10_reserved.txt.zip

Original Attachment has been moved to: mmdc_dump2_cre10_jedec.txt.zip

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