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Issue in setting  SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel

Question asked by Shabeer Badarudheen on Jan 13, 2017
Latest reply on Aug 28, 2018 by Shabeer Badarudheen

Hi All,

 

In our custom board, we have porting linux kernel from 3.10.17 to 4.1.15.
we are facing some issues with microphone custom audio driver (chip :ICS-43432, issue : missing some samples),which is working perfectly in 3.10.17.

 

We have compared the audio clocks in 3.10.17 and 4.1.15, both are different. In 3.10.17 clock values IMX6_AUDIO_I2S_BCK, IMX6_AUDIO_I2S_FRCK are 3.078MHz and 48.108KHz and in 4.1.15 it is 2.88MHz and 54 KHz.

 

Then we have compared the clock source code in both kernel (arch/arm/mach-imx/clk-imx6q.c ) and noticed some difference. We want to derive ssi1_sel clock from PLL4. In 3.10.17 code for that configuration is present but not in 4.1.15 . So i have tried to set this in 4.1.15 kernel using the function 'imx_clk_set_parent(clk[IMX6QDL_CLK_SSI1_SEL],clk[IMX6QDL_CLK_PLL4_AUDIO])',
but it gives an error at boot time, 'failed to set parent of clk ssi1_sel to pll4_audio: -22'.

 

may i know the reason for these error or how do we set/configure the parent clocks in 4.1.15?

Thanks,

Shabeer

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