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Flash ECC Test for the MPC5777C

Question asked by JONGMIN NA on Jan 12, 2017
Latest reply on Jan 17, 2017 by Peter Vlna

Dear NXP Engineers,

 

I want to make sure my Flash ECC Test is reasonable or nonsense.

 

This is a procedure of ECC Circuit test.

Flash ECC Circuit test always be executed only once during start up sequence.


1. The ERM configured that Flash related registers be enabled. ESCIE6, 7 and ENCIE6, 7


2. The Flash ECC error exception handler(ERM Isr) set through the OS configuraton.


3. Read a “failed” Flash location; the Flash ECC exception handler shall:

         Failed area : 0x400060 (UTEST area for the ECC test), So This area don’t affect a normal operating.

    
4. Above "Read" will generate an ECC exception.

5. ERM Isr will be invoked and There is no running reset. Because It is just test and I implemented that maintaining normal operating state without running reset.
6. We can get Flash ECC error status via ERM registers, such as EAR(Error Address Register)

 

Overall, My curious point is whether my Flash ECC test could be affect normal operating or It's OK.

Because even though this is just test, As you can see, EAR be set their error address... I worry that this test could affect the others.

 

Please let me know your opinion.

 

Best Regards,

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