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i.MX7D PCIe behavior of "Directed_Speed_Change" in "PCIE_PL_G2CR"

Question asked by Andrey Smirnov on Jan 12, 2017
Latest reply on Feb 6, 2017 by Richard Zhu



I am trying to understand the behavior of "Directed_Speed_Change" bit in "Gen2 Control Register (PCIE_PL_G2CR)" register (bit 17 and offset 0x700 + 0x10C) on i.MX7D. From reading the source code of PCIe driver in Freescale BSP (or mainline kernel) it appears that said bit is expected to be cleared by the hardware as a way of handshaking.


Experiments with i.MX6Q and i.MX7D variants of Sabre boards, though, show that when connected to a Gen 1 only peripheral (in my case external i210 PCIe card) i.MX6Q SoC will indeed clear said bit after it is written, where as i.MX7D SoC will not. Is that an expected behavior?