T1042 AVD and PAR1

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

T1042 AVD and PAR1

338 Views
gokulkrishnan
Contributor III

Hi,

In the reference design of T1042, I see that signals AVD and PAR1 from T1042 have been level translated and then given to the AVD pin of the NAND Flash. Can you confirm why you have dont this. It also talks about an interposer which is not clear to me.

Labels (1)
0 Kudos
1 Reply

270 Views
ufedor
NXP Employee
NXP Employee

Both mentioned signals are supplied from OVDD (1.8V) - refer to the processor's Data Sheet, Table 1. Pinout list by bus.

Obviously, a level translator is required if NAND Flash interface signals operate at 3.3V.

Interposer is a special module which is used in place of the processor to bing-up the development board.

0 Kudos