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T1042 AVD and PAR1

Question asked by Gokul Krishnan on Jan 12, 2017
Latest reply on Jan 12, 2017 by ufedor



In the reference design of T1042, I see that signals AVD and PAR1 from T1042 have been level translated and then given to the AVD pin of the NAND Flash. Can you confirm why you have dont this. It also talks about an interposer which is not clear to me.