I would like to ask about the configuration of PCIe related unused pins of i.MX6SoloX.
In case of not using PCIe, could you show me how PCIe related pins(PCIE_VP and PCIE_VPTX pins) should be treated?
Could you show me whether shoot-through-current can be prevented when disabling PCIe_LDOs?
From ‘Figure 10-12. Supplying i.MX 6SoloX power using integrated PMU’ in i.MX6SX reference manual(IMX6SXRM, Rev.1), my customer understands that PCIE_VPH, PCIE_VP and PCIE_VPTX pins should be connected to GND through capacitor when not used.
But according to its HW Devlopement Guide(IMX6SXHDG, Rev.1), the pins should be treated when not used as below.
- PCIE_VPH should be float or connected to ground directly when unused.
- PCIE_VP and PCIE_VPTX pins should be connected to GND through 4.7uF capacitors.
Could you show me which handling is the correct?