I want to ask you about CCM (Clock Controller Module).
I refer to the i.MX6DualLite Reference manual (IMX6SDLRM Rev.2).
It is described at P816 in RM as the follows.
For critical system bus clocks,･･･The mux for the serial clocks is not glitchless.
Are there any problem to write the same value on the bits of clock selector register and/or the bits of clock divider register without disable PLL and/or gating the input and output clocks?