Please explain below highlighted points 1,2,3.(yellow). This is processor expert code for FTM . In our code we are using this function with softwareTrigger =1 .
If the LDOK bit is set the CnV registers will be updated on next reload point, if the SYNCEN=1.
Assuming enhanced PWM synchronization (SYNCMODE = 1), if SYNCEN=1, the SW trigger causes CNV register updating either immediately (if SWRSTCNT = 1) or on next selected reload point (if SWRSTCNT = 0).
Thus the code you mentioned can cause CnV update on the same time (reload point) or probably 2 updates at different times depending on configured sync mechanism.
The latest driver version (EAR 0.8.2) does not include LDOK bit setting.
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