I am reviewing the i.MX 6SoloX architecture and I have some doubts with bus sharing. The Block Diagram shows and AXI and AHB Switch Fabric. I understood that the cores are connected to the PL301 by AXI or AHB and depending on the peripheral it uses the AHB or AXI. Is that correct?
Besides, PL301 can be configured as RR or LGR. However, is not possible to use both in parallel? Apart from that, how does the RDC module take part with the bus arbitration? Is posible to split the bus and the resources for each core?