AnsweredAssumed Answered

LVDS Display Output is sometimes shifted

Question asked by Christian Wiesner on Jan 9, 2017
Latest reply on Jun 15, 2018 by Christian Wiesner

I have trouble with the LVDS output of my i.MX6. Sometimes one bit of the LVDS Datastream is shifted, which leads to a flickering behaviour on the display side.


I can reproduce this error by stopping and starting the framebuffer:

echo 1 > /sys/class/graphics/fb0/blank
echo 0 > /sys/class/graphics/fb0/blank

If I do this ~15 times the error occurs and stays, until I repeat the commands above. What happens is attached in the two pictures in the attachement. Green and Yellow are my LVDS-Lines. ENABLE, HSYNC, VSYNC and DOTCLK are the output of my de-multiplexer.

  1. Normal.png is the normal state. HSYNC and VSYNC happen at the same time.
  2. Error.png is the error case. HSYNC and VSYNC don't happen at the same time. VSYNC is shifted from "Falling Edge" to "Rising Edge". There is an additional state on the LVDS Signal (Red Lines.


  • i.MX6 DualLite MCIMX6U5EVM10AB
  • Resolution: 1200x320
  • LVDS Clock 23MHz (x-clock 43.000)
  • VSYNC is LOW for 4 lines
  • HSYNC is LOW for 10 pixels
  • Left Margin: 150 Pixel
  • Right Margin: 150 Pixel

I would be happy about any hint where to look for the problem.


kind regards,