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How to reset DDR controller in T1024?

Question asked by veerendranath jakkam on Jan 9, 2017
Latest reply on Jan 12, 2017 by alexander.yakovlev

Hi ,

 

I am transferring control from u-boot to my bare board binary(which will execute from NOR flash). Now I want reset the DDR controller and re-initialize. I tried to reset using "DDR_DDR_SDRAM_CFG_3" reset but after i could not inialize RAM memory... Please refer below for my code... Pleas let me know if am doing anything wrong...

 

asm ("ddr_cntrl_reset:");
SET_GROUP_BASE(CCSRBAR + DDRC_GROUP_OFFSET);
//# DDR_SDRAM_CFG
CCSR_SET_W(0x110, 0x0);  // Disabling  DDR controller
//# DDR_SDRAM_CFG_3
CCSR_SET_W(0x260, 0x80000000); // Reset ddr controller.
//# wait for DDRC_RST bits to clear
asm ("xor 6, 6, 6");
asm ("oris 6, 6, 0x80000000@h");
asm ("ori 6, 6, 0x80000000@l");
asm ("ddr_reset_loop:");
CCSR_GET_W(0x260); // Will fetch the value to register 19
asm ("andis. 19, 19, 0x8000");
asm ("cmpw 19, 6");
asm ("bt eq, ddr_reset_loop");

asm ("ddr_cntrl_reset_end:");

 

// Re-initializing DDR
//# DDR_SDRAM_CFG
CCSR_SET_W(0x110, 0x67044000);
//# DDR_CS0_BNDS
CCSR_SET_W(0x000, 0x0000007F);
//# DDR_CS1_BNDS
CCSR_SET_W(0x008, 0x0000007F);
//# DDR_CS0_CONFIG
CCSR_SET_W(0x080, 0x80044302);
//# DDR_CS1_CONFIG
CCSR_SET_W(0x084, 0x80004302);
//# DDR_CS0_CONFIG_2
CCSR_SET_W(0x0c0, 0x00000000);
//# DDR_CS1_CONFIG_2
CCSR_SET_W(0x0c4, 0x00000000);
//# DDR_TIMING_CFG_3
CCSR_SET_W(0x100, 0x01071000);
//# DDR_TIMING_CFG_0
CCSR_SET_W(0x104, 0x50110004);
//# DDR_TIMING_CFG_1
CCSR_SET_W(0x108, 0xBCB48C56);
//# DDR_TIMING_CFG_2
CCSR_SET_W(0x10c, 0x0040C0D8);
//# DDR_SDRAM_CFG_2
CCSR_SET_W(0x114, 0x00401111);
//# DDR_SDRAM_MODE
CCSR_SET_W(0x118, 0x00441C70);
//# DDR_SDRAM_MODE_2
CCSR_SET_W(0x11c, 0x00980000);
//# DDR_SDRAM_MODE_4
CCSR_SET_DUP_W(0x204);
//# DDR_SDRAM_MODE_6
CCSR_SET_DUP_W(0x20C);
//# DDR_SDRAM_MODE_8
CCSR_SET_DUP_W(0x214);
//# DDR_SDRAM_MODE_3
CCSR_SET_W(0x200, 0x00001C70);
//# DDR_SDRAM_MODE_5
CCSR_SET_DUP_W(0x208);
//# DDR_SDRAM_MODE_7
CCSR_SET_DUP_W(0x210);
//# DDR_SDRAM_MD_CNTL
CCSR_SET_W(0x120, 0x00000000);
//# DDR_SDRAM_INTERVAL
CCSR_SET_W(0x124, 0x0C300100);
//# DDR_DATA_INIT
CCSR_SET_W(0x128, 0xDEADBEEF);
//# DDR_SDRAM_CLK_CNTL
CCSR_SET_W(0x130, 0x02000000);
//# DDR_INIT_ADDR
CCSR_SET_W(0x148, 0x00000000);
//# DDR_INIT_EXT_ADDR
CCSR_SET_DUP_W(0x14c);
//# TIMING_CFG_4
CCSR_SET_W(0x160, 0x00000001);
//# TIMING_CFG_5
CCSR_SET_W(0x164, 0x04401400);
//# DDR_ZQ_CNTL
CCSR_SET_W(0x170, 0x89080600);
//# DDR_WRLVL_CNTL
CCSR_SET_W(0x174, 0xC675F607);
//# DDR_SR_CNTR
CCSR_SET_W(0x17c, 0x00000000);
//# DDR_WRLVL_CNTL_2
CCSR_SET_W(0x190, 0x0808090B);
//# DDR_WRLVL_CNTL_3
CCSR_SET_W(0x194, 0x0C0D0E0A);
//# DDR_DDRCDR_1
CCSR_SET_W(0xb28, 0x80000000);
//# DDRCDR_2
CCSR_SET_W(0xb2c, 0x00000000);
//# DDR_ERR_DISABLE - DISABLE
CCSR_SET_W(0xe44, 0x00000000);
//# ERR_SBE
CCSR_SET_W(0xe58, 0x00000000);

//# delay before enable
asm ("lis 5, 0x0000");
asm ("ori 5, 5, 0x0fff");
asm ("mtspr 9 ,5");
asm ("wait_loop1:");
asm ("bc 16, 0, wait_loop1 ");

//# DDR_SDRAM_CFG
CCSR_SET_W(0x110, 0xE7044000);

//# wait for DRAM data initialization
asm ("lis 5, 0x0000");
asm ("ori 5, 5, 0x2ffd");
asm ("mtspr 9 ,5");
asm ("wait_loop2:");
asm ("bc 16,0,wait_loop2 ");

//# wait for D_INIT bits to clear
asm ("xor 5, 5, 5");
asm ("wait_loop3:");
CCSR_GET_W(0x114);
asm ("mr 5, 19");
asm ("rlwinm 5, 5, 0, 27, 27");
asm ("cmpwi 5, 0x0010");
asm ("bt eq, wait_loop3");

 

 

Regards,

Veerendranath

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