Why SNVS_LP register could not operate under non-OS for IAR IDE debug?

[hansonhe]

Dear, 

We could operator SNVS_LP register under U-boot mode, it could work, but after read or write this bit by IAR IDE, it could not work, could you help check whether have some setting problem? Thanks.

[igorpadykov]

Hi Hanson

one can check if snvs clocks are enabled in CCGR5 register,

please refer to sect.18.6.28 CCM Clock Gating Register 5 (CCM_CCGR5)

i.MX6UL Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf

Best regards
igor
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[hansonhe]

Dear，

snvs clocks have enabled in CCGR5 register, but it still have the same problem，whether need other special setting？or do you have the reference code for it in IAR IDE？

[igorpadykov]

Hi Hanson

in general one can dump/compare registers in uboot/IAR, pay attention to
AIPSTZ and CSU registers, SNVS_LP permissions settings is CSL3 [23:16],
described in i.MX6UL Security Reference Manual (to obtain copy please create service request).

Unfortunately on i.MX6UL platform IAR IDE is not officially supported tool by NXP, it is developed

and supported by IAR. Supported only Linux/Uboot.

One can to apply to NXP Professional Services for developing such kind of applications

http://www.nxp.com/support/nxp-professional-services:PROFESSIONAL-SERVICE

Best regards
igor

[hansonhe]

Ok, the issue is closed.

[hansonhe]

Dear， could you help send i.MX6UL Security Reference Manual to my mail: ciang.he@nxp.com, thanks.