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How to reduce inter-byte delay in ECSPI of i.MX 6SoloX cortex M4

Question asked by manikandan P S on Jan 8, 2017
Latest reply on Jan 10, 2017 by manikandan P S


I am using ECSPI of i.MX 6SoloX in M4 core. The application is executing in OCRAM. ECSPI is configured as master for 1MHz speed, ecspiClockPhaseSecondEdge,ecspiClockPolarityActiveHigh with the following additional register settings:


Start Mode Control is enabled in ECSPI_CONREG_REG;

SS_CTL is enabled in master mode;


I have a byte array of 13 bytes ( formatted in little endian ) with values ranging from 0 to 12. I need to shift this out via ECSPI starting from 0 to 12. Since the hardware fifo is 64 words wide, i selected BURST_LENGTH in ECSPIx_CONREG as 7 for single byte burst and i i write into ECSPIx_TXDATA register continously without checking the status on ECSPIx_STATREG register but, i see ~ 5 micro second delay between each byte in the clock, chip select is continuous for the entire transaction (13 bytes) though.  If i have to increase the BURST_LENGTH field then, i need to do the endian conversion.  Where is this 5 micro second delay coming from ? is this the burst delay ? how to avoid this delay ? Actual transaction is as below:

but the expected (this is from a different make) is this: 



Manikandan P S