EMC test result show DDR CLK 396MHz and 1080MHz is higher than limit. and 352M, 1056M and 1408M related to LVDS CLK 50MHz are also higher than limit. I want to SSC to DDR clk and LVDS clk to reduce the radiation for these frequency points.
But I can't find the related information in i.mx6 dl datasheet. Does anybody have the experience on this?