From the reference manual of the i.MX6(Q) board, we can see that the OCRAM can be splitted in two, having the end (from START_ADDR to the end of the OCRAM) of the memory protected by a TZASC. The configuration of the start address and the activation of the feature is done i IOMUX GPR10 register.
It is also explained that the security policy (S / NS, User vs Priv) should be programmed in the CSU.
However, I didn't found any occurrences of the OCRAM in the CSU CSL registers from the Security RefMan. Also the "OCRAM Trustzone" section of the security manual makes reference to a CSU section which is not in the document.
- Can someone point me to the correct input to correct location to learn which CSU register I need to configure for this purpose ?
- We can also find in the IOMUX GPR10 register a bit called SEC_ERR_RESP. I'm not sure which security response it refers to ? Is it only for the Secure OCRAM access or is it used elsewhere ?