We are currently looking at the iMX6UL processor specifications to see if it suits our application. One of our constraints concerns the maximum bit rate of SAI devices in slave mode (SAI_BCLK). In the processor datasheet the minimum period of this signal is 4 x tsys (see S11 in Table 73 on page 85) but tsys is not specified. Can you tell me the value of this time?
For the KL28Zxxx processors the minimum period of this signal is 80 ns. Can we assume that the iMX6UL has the same specifications?