I am using SC16IS762 in my design.
Vdd = 3.3V
Serial data on RX input 0-2.5V @ 500kbit/s
From the datasheet : Vih_min = 2.0V and Vil_max = 0.8V
Problem: I have a high impedance on the RX input of the component due to other constraints, so my bits rise and fall time are not very good and the component can have trouble detecting 0 and 1.
Datasheet says the clock is 16x faster than the bitrate, but no information is given regarding the minimum slew rate for 500kbit/s in order to guarantee good detection of the bits.
In other terms, we don't know when the sampling is made during the bit.
Do you have information regarding the minimum slew rate ?
Or the sampling point of the component (middle of bit ? 75% of bit ? 25% of bit ?)
I would like to know how much I need to improve the shape of the bits and the margin I can have regarding the slew rate.
Thank you in advance for your answer.