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How to use two Ethernet ports at same time on i.MX6UL

Question asked by Andy Chien on Jan 4, 2017
Latest reply on Jan 12, 2017 by Carlos_Musich

Dear Sir,

 

Our customer used i.MX6UL and want to run two Ethernet function, but find pads define question.

We see NXP BSP and run i.MX6UL EVK is only workable one Ethernet now.

Could you tell us how to work two Ethernet at same time on i.MX6UL?

Thanks

 

i.MX6UL RM pad define

 

i.MX6UL EVK

 

 

 i.MX6UL BSP pin define ethernet phy, device tree 

                      pinctrl_enet1: enet1grp {

                                 fsl,pins = <

                                            MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN        0x1b0b0

                                            MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER         0x1b0b0

                                            MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00      0x1b0b0

                                            MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01      0x1b0b0

                                            MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN         0x1b0b0

                                            MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00       0x1b0b0

                                            MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01       0x1b0b0

                                            MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1           0x4001b031

                                 >;

                      };

 

                      pinctrl_enet2: enet2grp {

                                 fsl,pins = <

                                            MX6UL_PAD_GPIO1_IO07__ENET2_MDC              0x1b0b0

                                            MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0

                                            MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN        0x1b0b0

                                            MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER         0x1b0b0

                                            MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00      0x1b0b0

                                            MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01      0x1b0b0

                                            MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN         0x1b0b0

                                            MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00       0x1b0b0

                                            MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01       0x1b0b0

                                            MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2           0x4001b031

                                 >;

                      };

 

only define pinctrl_enet2MDIO/MDC pin, &fec2 define mdio interface

&fec1 {

           pinctrl-names = "default";

           pinctrl-0 = <&pinctrl_enet1>;

           phy-mode = "rmii";

           phy-handle = <&ethphy0>;

           status = "okay";

};

 

&fec2 {

           pinctrl-names = "default";

           pinctrl-0 = <&pinctrl_enet2>;

           phy-mode = "rmii";

           phy-handle = <&ethphy1>;

           status = "okay";

 

           mdio {

                      #address-cells = <1>;

                      #size-cells = <0>;

 

                      ethphy0: ethernet-phy@2 {

                                 compatible = "ethernet-phy-ieee802.3-c22";

                                 reg = <2>;

                      };

 

                      ethphy1: ethernet-phy@1 {

                                 compatible = "ethernet-phy-ieee802.3-c22";

                                 reg = <1>;

                      };

           };

};

 

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