I used MPC5777C for my application.
Our OEM want to disable the cache for SRAM.
I mean SRAM cache inhibited via MMU TLB configuration.
I supposed that their intend(cache inhibit) is data coherency between core 0 and core 1.
But, I think It can be achieved by Data coherency bit at mas2. Isn't it?
In other words, Even though apply cache for SRAM, Prevent some corrupted data between cores If data coherency bit is set.
Actually, I imlemented data copy routine from core 1 to core 0. There is little bit large data and so that copying time is 100us when cacheable. But cache disabled then 230us takes approximately.
So I think I can get more effective performance through the cache.
Or If there is other side effect, Please let me know.